High performance Carbon Nanotube (CNT) Field Effect Transistors (FETs) have been demonstrated in the art. See, for example, the following references, which are all incorporated herein by reference: I. Radu et al., “Oriented Growth of Single-Wall Carbon Nanotubes Using Alumina Patterns,” Nanotechnology, Vol. 15, pp. 473-476 (Feb. 2, 2004); S. Li et al., “Silicon Nitride Gate Dielectric for Top-Gated Carbon Nanotube Field Effect Transistors,” J. Vac. Sci. Technol. B, Vol. 22, No. 6, pp. 3112-3114 (Dec. 10, 2004); A. Yu, “A Study of Carbon Nanotubes and Their Applications in Transistors,” School of Electrical and Computer Engineering, 1-32 (May 17, 2004) (published at http://132.236.67.210/engrc350/ingenuity/Yu_A_paper_issue—3.pdf); “Carbon Nanotubes and Nanotube Transistors,” ECE497NC Lecture 14, 1-9 (Mar. 10, 2004) (published at http://www.crhc.uiuc.edu/ece497nc/scribe/nanotube1.pdf); A. Javey et al., “Carbon Nanotube Field-Effect Transistors with Integrated Ohmic Contacts and High-K Gate Dielectrics,” Nano Letters, Vol. 4, No. 3, pp. 447-450 (Feb. 20, 2004); S. Heinze et al., “Electrostatic Engineering of Nanotube Transistors for Improved Performance,” Applied Physics Letters, Vol. 83, No. 24, pp. 5038-5040 (Dec. 15, 2003); A. Javey et al., “Advancements in Complementary Carbon Nanotube Field-Effect Transistors,” IEDM Tech. Digest., pp. 741-74 (2003); J. Guo et al., “Performance Projections for Ballistic Carbon Nanotube Field-Effect Transistors,” Applied Physics Letters, Vol. 80, No. 17, pp. 3192-3194 (Apr. 29, 2002); X. Liu et al., “Carbon Nanotube Field-Effect Inverters,” Applied Physics Letters, Vol. 79, No. 20, pp. 3329-3331 (Nov. 12, 2001); R. Martel et al., “Single- and Multi-Wall Carbon Nanotube Field-Effect Transistors,” Applied Physics Letters, Vol. 73, No. 17, pp. 2447-2449 (Oct. 26, 1998).
As these prior approaches make clear, a CNT FET, like a traditional FET, comprises a gate, a source, and a drain. A carbon nanotube, or a plurality of carbon nanotubes, span(s) lengthwise between the source and the drain such that an end of each tube(s) is in contact with the drain and source. Accordingly, the carbon nanotube(s) comprise(s) the conductive media or “channel” for the CNT FET.
One problem with this design of CNT FETs is control of the “off current” of such devices. Specifically, a CNT FET should ideally draw no or negligible current between the source and the drain when the device is off, i.e., when no potential is applied to the gate and despite the presence of a typical voltage on the drain of the device. However, such ideal performance is difficult to achieve due to modulation of the barrier heights at the CNT/source-drain interface. In short, CNT FETs tend to leak drain current when a voltage is applied to the drain, but no voltage is applied to the gate.
One proposed solution to this problem in CNT FETs has been to use a gate which is asymmetric with respect to the drain and the source. More specifically, it has been proposed to move the gate away from the drain and towards the source to minimize barrier height modulation at the drain. For example, such an approach was postulated in S. Heinze et al., “Electrostatic Engineering of Nanotube Transistors for Improved Performance,” Applied Physics Letters, Vol. 83, No. 24, pp. 5038-5040 (Dec. 15, 2003), which was incorporated by reference above. However, a review of this reference shows that the asymmetric devices there illustrated are hypothetical in nature. In short, while useful to illustrate the problem of symmetric gates, and the possible solution of asymmetric gates, this reference does little to illustrate how such a device can be fabricated in any sensible, practical, or cost-effective way.
If the benefits of asymmetric gates in CNT FETs are to be realized, efficient manufacturing methods will need to be developed. This is non-trivial, especially when the importance of self aligned processes are understood. Generally, to promote uniformity in the performance of transistors, self aligned techniques are used to ensure that the source and drain will be automatically aligned with the gate. In a simple example, a self aligned process in the fabrication of a transistor might comprise patterning the transistor gate and then using that gate as a mask for the source/drain ion implants. By use of a self aligned process, it can be assured that all of the transistors fabricated will roughly operate in the same fashion. Consider by contrast a non-self aligned transistor fabrication process in which source and drains are fabricated first, followed by patterning of the gate. Due to process variations and inconsistencies in the alignment of the gate from transistor to transistor, one could not expect the drain-to-source current to be very uniform from transistor to transistor. Additionally, use of such a non-self aligned process makes a particular transistor fabrication process difficult to scale to smaller geometries.
In short, what is needed in the CNT FET art is a transistor fabrication process that: allows for the provision of an asymmetric gate; is efficient and cost effective; preferably uses standard fabrication procedures; is self aligned; and is scalable. This disclosure presents embodiments of such a solution.